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21.3.3.5 Debug
If DEBUGRUN in LETIMERn_CTRL is cleared, the LETIMER automatically stops counting when the
CPU is halted during a debug session, and resumes operation when the CPU continues. Because of
synchronization, the LETIMER is halted two clock cycles after the CPU is halted, and continues running
two clock cycles after the CPU continues. RUNNING in LETIMERn_STATUS is not cleared when the
LETIMER stops because of a debug-session.
Set DEBUGRUN in LETIMERn_CTRL to allow the LETIMER to continue counting even when the CPU
is halted in debug mode.
21.3.4 Underflow Output Action
For each of the repeat registers, an underflow output action can be set. The configured output action is
performed every time the counter underflows while the respective repeat register is nonzero. In PWM
mode, the output is similarly only changed on COMP1 match if the repeat register is nonzero. As an
example, the timer will perform 7 output actions if LETIMERn_REP0 is set to 7 when starting the timer
in one-shot mode and leaving it untouched for a while.
The output actions can be set by configuring UFOA0 and UFOA1 in LETIMERn_CTRL. UFOA0 defines
the action on output 0, and is connected to LETIMERn_REP0, while UFOA1 defines the action on output
1 and is connected to LETIMERn_REP1. The possible actions are defined in Table 21.2 (p. 294) .
Table 21.2. LETIMER Underflow Output Actions
UF0A0/UF0A1
00
01
10
11
Mode
Idle
Toggle
Pulse
PWM
Description
The output is held at its idle value
The output is toggled on
LETIMERn_CNT underflow if
LEIMERn_REPx is nonzero
The output is held active for one clock
cycle on LETIMERn_CNT underflow if
LETIMERn_REPx is nonzero. It then
returns to its idle value
The output is set idle on
LETIMERn_CNT underflow
and active on compare match
with LETIMERn_COMP1 if
LETIMERn_REPx is nonzero.
Note
For the Pulse and PWM modes, the outputs will return to their idle states regardless of the
state of the corresponding LETIMERn_REPx registers. They will only be set active if the
LETIMERn_REPx registers are nonzero however.
The polarity of the outputs can be set individually by configuring OPOL0 and OPOL1 in
LETIMERn_CTRL. When these are cleared, their respective outputs have a low idle value and a high
active value. When they are set, the idle value is high, and the active value is low.
When using the toggle action, the outputs can be driven to their idle values by setting their respective
CTO0/CTO1 command bits in LETIMERn_CTRL. This can be used to put the output in a well-defined
state before beginning to generate toggle output, which may be important in some applications. The
command bit can also be used while the timer is running.
Some simple waveforms generated with the different output modes are shown in Figure 21.6 (p.
295) . For the example, REPMODE in LETIMERn_CTRL has been cleared, COMP0TOP also in
LETIMERn_CTRL has been set and LETIMERn_COMP0 has been written to 3. As seen in the figure,
LETIMERn_COMP0 now decides the length of the signal periods. For the toggle mode, the period of the
output signal is 2(LETIMERn_COMP0 + 1), and for the pulse modes, the periods of the output signals
2011-04-12 - d0001_Rev1.10
294
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